More aggressive functional scaling and increasingly complex transistor structures have steadily increased process complexity, increasing the risk that a specified pattern cannot be manufactured with acceptable yields.
A single layer requires more process steps, each with more tunable parameters than ever before. To help manage design risks, Foundries provides detailed designs of manufacturing (DFM) rules and informs designers of patterns to avoid. However, the number of DFM rules for cutting-edge processes can overwhelm traditional design methods.
It may be impossible to design that meets all casting requirements at the same time. In that case, the model fails to converge. Even if the solution exists, it may require unrealistic amounts of calculation time.
Kostas Adam, Synopsys' vice president of engineering and head of the company's Mask Solutions team, explained that machine learning technology based on neural networks can enhance or replace traditional compact models. It helps identify patterns that pose important design risks, find causal effects relationships, and modify designs to limit risk.
Among other things, DFM constraints affect design power, performance, and area (PPA) trade-offs. The simplest solution to DFM violations is often to move further away from the affected devices, but there are rarely any solutions with the best results of PPA. On the other hand, achieving an aggressive PPA target may require accepting more design risks and potentially lower yields. However, assessing these interactions can be extremely difficult. Especially during the early process development stage where actual designs are rarely available. It is difficult to improve design rules without testing realistic designs.
Find and fix hotspots
In a presentation at this year's SPIE Advanced Lithography and Patterning Conference, Geng Han, a research staff member at IBM Research, said that the root cause of defect hotspots lies between interactions between layers and process steps. Process development test vehicles are inevitably limited, time-consuming, and do not always identify potential issues. Therefore, Han proposed to enhance the traditional test vehicle using synthetic layout generation.
The guided machine learning model generated test patterns attached to the proposed design rules. Composite layouts need not be functional electronically, and can target specific layout densities, specific types of line ends, and more. These patterns can be simulated by lithographic models and rendered in silicon or both to identify the patterns that are most likely to produce defects. This information can be used to improve the process and update design rules. [1]
Still, Samsung's Process Integration Engineer Jinah Kim explained that PPA optimization in a design is an iterative process. Designers need to manually adjust design parameters, perform the location and route (P&R) process, and evaluate the results. For 8,000 square micron blocks, approximately 1,200 cpu time is required to evaluate 50 different design conditions. Instead, Kim's group considered the effects of PPA and proposed an alternative methodology to produce parallel effects.
Samsung's method depends on Cadence's Cerebrus. Cadence's Cerebrus is an AI-driven chip design automation tool that allows designers to specify primitives such as switching power and power leakage, depending on their goals. To train a machine learning model using only these primitives, you must ensure that the resulting design meets the PPA target. Celebras then generates a design scenario by applying the proposed DFM rules to the models created in the first phase. By ensuring that the proposed design already meets the PPA target, this approach reduced the evaluation time of 8,000 square microns to just 90 cpu hours, improving 13 times. [2]
In contrast, using the P&R tool to fix DFM rule violations is ineffective as there are many of them. Instead, Lynn Wang, a key member of GlobalFoundries' technical staff, and her colleagues, used machine learning tools to group similar geometric features of reference designs, and combined these “problem” patterns with human-designed solutions to build a pattern library. By adding this library and its related models to the P&R Hotspot Repair Tool, the tool was able to automatically fix 81% of DFM violations. In their tests, this approach was 50 times faster than rerouteing layers. [3]
Jonathan Ho, a senior member of the AMD technical staff, said predicting defect hotspots from design polygons alone can lead to many false positives. Simulating wafer functionality using process parameters is difficult because the number of parameters is enormous and not all affect the wafer pattern. Instead, HO observed that the shape of the post-etch feature was the sum of all processes from initial resist coating and exposure throughout the development and etching process. A physical feature is that post-etch patterns can also be identified and measured relatively easily. Therefore, in collaboration with the AMD Group (Siemens EDA) we use a reinforced learning model to identify potential hotspots based on design patterns and pattern similarities known from silicon, resulting in defects. [4]
Yen next year's yield, today's yield
As devices move from design to production, the next challenge is to achieve the yields promised by estimating design risk. Both the process and its associated defects evolve over time. Device behavior can cause chemicals to age. Continuous improvement efforts can shift the process window.
Semiai CEO Taekwon Jee tried to capture both general issues and historical fixes in a structured way. His team used their own digital twin tool, Prism, to collect raw process sensor data and tagged it with tools, processes, layers, and other contextual information. The hybrid neural network transformer model extracted causal relationships between variables. Meanwhile, the company's inference semantic inference engine used a large-scale language model (LLM) trained on structured publication reports, including root causes and corrective actions. By linking this data to the PRISM database, JEE was able to link past issues to relevant sensor data. The next step, automatic failure prediction, flagged new anomalies in the current data and linked them to historical fixes for similar issues. [5]
At this stage, surveillance of humans is important, Zee said. Many proposed fixes actually solved the problem, but about 5% did not resolve it, especially in ambiguous situations. That 5% can easily lead to losses in production, or even exacerbate the underlying problem.
Artificial intelligence with no hype
Over the past few years, AI has been built up into public consciousness thanks to the rise of ChatGPT and other LLM-based tools. Opinions run from what Openai CEO Sam Altman called “the most powerful technology humans have ever created” to environmentally destructive plagiarism machines.
But far from the mass media spotlight, machine learning tools help humans by computers doing their best. In other words, it collects, manages and analyzes the vast amount of data generated by modern industrial processes. So, while AI is causing controversy, machine learning is rapidly becoming an important part of designer toolkits.
reference
- Geng Han, et al. , “Generating Guided Random Synthesis Layouts and Machine Learning-Based Defect Prediction for Leading Edge Technology Node Development,” DTCO and Computational Pattarning IV, Neal V. Lafferty, Harsha Grunes, Proc. Spie Vol. 13425, 1342509 doi: 10.1117/12.3051134
- Jina Kim, “New DTCO Framework to harness machine learning for comprehensive PPA-Y optimization,” DTCO and Computational Pattarning IV, Neal V. Lafferty, Harsha Grunes, Proc. Spie Vol. 13425, 134250K doi: 10.1117/12.3051595
- Lin T.-N. Wang, et al. , “Optimization of Machine Learning Assistance Patterns to Fix Designs for Manufacturing Possibility (DFM) Rule Check Violations,” DTCO and Computational Pattarning IV, Neal V. Lafferty, Harsha Grunes, Proc. Spie Vol. 13425, 134250a doi: 10.1117/12.3051488
- Jonathan Ho, et al. , “Improved multi-layer process defect prediction accuracy for artificial intelligence/machine learning (AI/ML) platforms,” DTCO and Computational Pattarning IV, Neal V. Lafferty, Harsha Grunes, Proc. Spie Vol. 13425, 134250N doi: 10.1117/12.3051562
- Teekwon Jee, “LLM-based overlay problem classification and solution optimization in semiconductor manufacturing,” DTCO and Computational Pattarning IV, Neal V. Lafferty, Harsha Grunes, Proc. Spie Vol. 13425, 134251d doi: 10.1117/12.3050976
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