Live demonstrations of industry-leading RISC-V solutions and CPU IP are all on display at Booth #8. Check out the latest advancements from Andes' presentations and posters.
Munich, Germany – June 21, 2024 – Andes Technology Corporation, a leading provider of high-efficiency, low-power 32/64-bit RISC-V processor cores and a founding Premier Member of RISC-V International, is pleased to announce its participation at RISC-V Summit Europe 2024, the prestigious annual event taking place in Munich from June 24-28, 2024. As a key contributor, Andes will have a presentation highlighting its comprehensive lineup of RISC-V IP as well as showcasing cutting-edge RISC-V developments in a poster session. At Booth #8, Andes will demonstrate its leadership in AI and automotive technologies and showcase its latest QiLai SoC and development board for RISC-V SW development.
Frankwell Lin, Chairman and CEO of Andes, will highlight Andes RISC-V IP portfolio, robust partner ecosystem and latest processors such as automotive-grade ISO26262 certified cores and out-of-order CPUs in his demo theater talk “Andes' High-Value RISC-V Processors and Their Applications” on June 25th at 1:10pm. Chunnan Ke, Senior Technical Manager at Andes, will provide details on how RISC-V's matrix extensions and customized quantization instructions can improve common convolutional neural network (CNN) applications in his presentation “Enhancing Convolutional Neural Network Computations with Integrated Matrix Extensions” on June 25th at 12:15pm. Finally, Vince Wu, Sales Manager at Andes, will share compelling customer success stories in his demo talk “Andes RISC-V Everywhere in Our Lives!” on June 25th at 4:20pm.
Andes, a key player in the RISC-V community, will be showcasing four posters in the poster session. Topics covered include Andes' ecosystem approach to accelerate RISC-V adoption in automotive, insights into IOPMP, MobileBERT on RISC-V, and integrated matrix extensions. Visit and interact with Andes speakers to gain deeper insights into how these technologies are shaping and revolutionizing RISC-V computing.
The display of QiLai SoC and Voyager development board was one of the highlights of the event. QiLai SoC contains a high-performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. Voyager is a 9.6″ x 9.6″ Micro ATX form factor development board that contains QiLai SoC and a host of peripherals. AndesCore™ AX45MP superscalar multicore includes 2MB Level 2 cache and MMU (Memory Management Unit) for Linux-based applications. AndesCore™ NX27V vector processor supports a full range of RISC-V standard and Andes extended data types optimized for AI workloads. Fabricated on TSMC's advanced 7nm process technology, the QiLai SoC and its Voyager development board are a live demonstration of Andes' commitment to enabling RISC-V software development. The QiLai SoC and Voyager development board will be on display at both the Andes booth and in the Developer Zone. Don't miss this chance to see a first look at Andes' cutting-edge RISC-V technology.
In addition, Andes will proudly display development boards powered by customers with AndesCore-based SoCs at Booth #8. These boards include Tinker V, the first RISC-V single-board computer (SBC) from ASUS IoT, an MPU development board from Renesas, and an AI development kit with camera module from Canaan. Please visit Booth #8 to have one-on-one discussions with Andes experts and experience live demonstrations of advanced CPU IP technologies.
Details of Andes’ session at RISC-V Summit Europe include:
Tuesday, June 25
- 12:15-12:30 PM: Presentation: “Enhancing Convolutional Neural Network Computation with Unified Matrix Expansion” Chunnan KeSenior Technical Manager
- 1:10-1:20 PM: Demo Theater Talk “Andes' High Value RISC-V Processor and its Applications” Frankwell LinChairman and CEO
- 4:20pm: 2-minute lightning talk: “Andes RISC-V, Everywhere in Our Lives!” Vince Wusales manager
- All day: Poster “Andes Ecosystem Approach to Accelerate RISC-V Adoption in Automotive Design” Samuel ChanDeputy Marketing Director
- All day: Poster “Deep Insights into IOPMP: Priority and Non-priority Rules” Paul KuDeputy Director
Thursday, June 27
- All day: Poster “MobileBERT on RISC-V: Softmax Acceleration using IREE Compiler and ACE-RVV Extensions” Yuefeng LiManager of Computing Acceleration Division
- All day: Poster “Enhancing Convolutional Neural Network Computations with Integrated Matrix Expansion” Chunnan KeSenior Technical Manager
For more information, visit the RISC-V Summit Europe website.
About Andes Technology
With 19 years of business experience and a founding Premier member of RISC-V International, Andes is a publicly listed company (TWSE: 6533, SIN: US03420C2089, ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a driving force in bringing RISC-V into the mainstream. The company's V5 RISC-V CPU family ranges from small 32-bit cores to advanced 64-bit out-of-order processors with DSP, FPU, vector, Linux, superscalar, functional safety and multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs will exceed 14 billion. For more information, please visit https://www.andestech.com.
