Imperas RISC-V reference models, simulators, test and verification IP combined with Cadence SystemVerilog simulation tools to provide an integrated RISC-V verification solution
Oxford, United Kingdom, 10th July 2023 — Imperas Software Ltd., a leader in RISC-V simulation solutions, today announced that Cadence Design Systems, Inc. (Nasdaq: CDNS) has teamed up with Imperas to develop functional safety solutions for NSITEXE, Inc., a Denso Group company. and development of RISC-V based processor IP for next generation embedded systems. The ImperasDV RISC-V processor verification solution is fully compatible with the full Cadence verification flow including the Xcelium Logic Simulator and Verisium artificial intelligence (AI) driven platform for debug, analysis and management.
Impeller DV is the industry-leading RISC-V processor verification solution. Lockstep continuous comparison methodology. This enables both accurate problem detection and efficient resolution of discrepancies between the design under test and the Imperas RISC-V reference model.of cadence xerium Logic Simulator provides a SystemVerilog simulation environment, including the tightly integrated high-performance interfaces necessary to work effectively with ImperasDV. Used with Cadence SimVision debug and analysis tools, they provide an integrated environment for comprehensive verification of NSITEXE Akaria processor IP, including NS72, an out-of-order 64-bit RISC-V processor with RVV vector extensions. create. .
With its open-standard Instruction Set Architecture (ISA), RISC-V offers processor developers many options and configurable features, enabling the development of optimized, domain-specific processors. Impeller DV Perform RISC-V design verification tasks and tasks across the complete specification using Imperas RISC-V reference models, architectural verification tests, additional functional test suites, coverage analysis, and simulation-based testing methodologies for asynchronous events and debug operations. Supports custom instructions. .
“Developed using Imperas RISC-V verification technology and Cadence’s leading SystemVerilog simulator and debug tools, the NSITEXEAKARIA processor is intended to address the high-performance requirements of AI and automotive requirements.” It contains the features and qualities necessary to achieve the ISO 26262 ASIL D functional safety standard in addition to being an efficient processor optimized for next-generation embedded applications.” Mr. Hideki Sugimoto, CTO, NSITEXE Co., Ltd., a Denso Group company. “Since NSITEXEAKARIA processors are being adopted in a wide range of next-generation automotive, safety-critical and embedded applications, the verification methodology supported by Imperas and Cadence is invaluable in meeting quality targets and on-time development schedules. ”
“By integrating our Xcelium Logic Simulator with Imperas’ RISC-V verification technology, NSITEXE will be able to design next-generation Akaria processors optimized for safety-critical applications and compliant with the ISO 26262 ASIL D standard. “It’s been a long time coming,” said Paul Cunningham, general manager of Cadence’s Systems & Validation Group. “Our collaboration demonstrates Cadence’s commitment to collaboration and innovation to support our customers in the rapidly evolving semiconductor industry.”
“Processor verification is difficult, but essential for RISC-V deployments,” he said. Simon Davidmann, CEO of Imperas Software Ltd. “ImperasDV is the first commercially available RISC-V processor verification solution, and achieving tight integration with Cadence is key to NSITEXE’s successful use of ImperasDV.”
Case study published
Cadence, Imperas, and NSITEXE released details about the design flow and implementation. Lockstep continuous comparison RISC-V verification methodology as a case study. This case study describes the NSITEXE RISC-V processor IP, including the verification challenges of the NS72 architecture, the lockstep consecutive comparison verification technique used for processor DV, and an example of bugs avoided using this technique. increase. This case study details the integration of the Imperas and Cadence tools used and the complete validation flow.
This case study is now available at https://www.imperas.com/docs.
availability
of Impeller DV RISC-V processor verification technology is already in active use with many large customers, some of whom have working silicon prototypes and are currently working on their second generation designs. These customers, partners and users span a wide range of RISC-V adopters, from open source to commercial, research to industrial, microcontrollers to high performance computing.These handpicked samples include: Codasip, Dolphin Design, EM Microelectronics (Swatch), Frontgrade Gaisler, Intrinsix, NSITEXE (Denso), NVIDIA Networking (Mellanox), NXP, OpenHW Group, MIPS, Seagate Technology, Silicon Labsand Baltrix systemIn addition, there are many more that have not yet been published. ImperasDV is available now. For more information, visit Imperas.com/ImperasDV.
RISC-V Verification Interface – RVVI
To leverage investments in verification IP and test infrastructure, an open standard RISC-V Verification Interface (RVVI) has been introduced by many commercial developers and open source projects (such as the OpenHW project in the CORE-V IP roadmap). has been adopted by core. RVVI provides a standard interface for connecting the RISC-V processor RTL to the testbench via tracer. It also defines a standard API for RISC-V verification IP that supports lockstep sequential comparison techniques. The flexibility of RVVI supports the full range of RISC-V specifications and features, increasing the capability level of designs with privileged modes, vector extensions, out-of-order pipelines, multi-threading, multi-hearts, and multi-issues. You can hire as you go. In addition, it also includes user-defined custom instructions and extensions. RVVI supports his RISC-V innovation with verification IP and the flexibility needed for reuse as the DV team scales up to support the rapid growth of RISC-V verification projects. . For more information and downloads, see https://github.com/riscv-verification/RVVI.
free riscvOVPsimPlus A package containing the Imperas RISC-V reference model, the latest test suite, and instruction coverage analysis with the latest RISC-V certification specification updates is now available at OVPworld (www.OVPworld.org/riscvOVPsimPlus).
DAC 2023 – July 9-13, 2023, San Francisco, CA
Visit Cadence (booth 1511) and Imperas (booth 2336) for demonstrations and discussions during DAC 60.
About the impeller
Imperas is a leading provider of RISC-V processor models, hardware design verification solutions and virtual prototypes for software simulation. Imperas works with an Open Virtual Platform (OVP) to provide a wide variety of processors, IP vendors, CPU architectures, system IP, and processor and system reference platforms, from simple single-core bare-metal platforms to fully heterogeneous Facilitate availability of open source models for models. A multi-core system booting SMP Linux. All models are available from Imperas (www.imperas.com) and the Open Virtual Platforms (OVP) website.
For more information on Imperas, please visit https://www.imperas.com/.
