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Signaloid previews new ASIC built specifically for physical AI and robotics workloads.
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The chip is being taped out with TSMC in partnership with imec and Cadence’s IC-Link, and is expected to deliver up to 1000x better performance per watt for key physical AI workloads.
Cambridge, UK, June 2, 2026–(BUSINESS WIRE)–Signaloid (https://signaloid.com), a computing platform company providing hardware and binary translation-based acceleration of AI, robotics, aerospace, and quantitative finance workloads, today announced tapeout and preliminary specifications for its C0-ASIC. Delivery of the first customer engineering samples is scheduled for Q3 2026, and additional FPGA-based systems implementing the ASIC design are being discussed for deployment in the UK and Switzerland in late 2026.
C0-ASIC specifically targets energy-efficient physical AI workloads. The UK Advanced Research and Inventions Agency (ARIA) will accept deliveries of ASIC-based systems for use in next-generation AI workloads such as quadratic methods.
“ARIA’s Scaling Compute program has commissioned several innovative technology prototypes that explore unconventional ideas to design new AI accelerators.” ARIA Program Director Suraj Bramkhaval said: ”We commissioned Signaloid’s C0-ASIC to evaluate randomized numerical linear algebra and stochastic computing workloads. We believe that randomized linear algebra is a fundamentally new and powerful technique that underpins many applications in computer science, including AI, and leveraging these principles in hardware has the potential to provide entirely new vectors for improving performance. We are excited to partner with Signaloid to invest behind this theme and explore its full potential. ”
Different types of AI computing accelerators
The C0-ASIC is Signaloid’s distribution-enhanced computing hardware (UxHw®) Technology.
Unlike traditional CPUs and GPUs, which use vast amounts of computational power across thousands of computational cores to solve problems that require iterative randomized variations, Signaloid’s UxHw dynamically restructures computations based on new mathematical techniques to achieve the same results while often using 1000 times (or more) less energy.
UxHw technology and its implementation is covered by a growing portfolio of over 90 intellectual property applications in the US, China, Taiwan, Japan and the EU.
international partnership
The design and implementation is the result of a collaboration between Signaloid and world-leading design partners IC-Link by imec and US-based Cadence Design Systems.
