A new type of computer component developed by researchers at the University of California, Santa Barbara and Tohoku University in collaboration with Taiwan Semiconductor Manufacturing Company (TSMC) could dramatically improve the efficiency of artificial intelligence and machine learning. This technique is based on “probability bits” or “p-bits,” which are hardware elements that naturally vary between 0 and 1. Unlike traditional digital bits, which have a fixed value, p-bits can efficiently explore many possibilities. This makes them suitable for solving problems that are difficult for traditional computers, such as optimization and inference.
Until now, most p-bit designs required analog electronic components to control how often the output was 0 or 1. These analog components, called digital-to-analog converters (DACs), are bulky, power-hungry, and expensive, hindering scalability. The new work offers a breakthrough: a fully digital p-bit design that eliminates the DAC completely.
“Reliance on analog signals has hindered progress,” says Shunsuke Fukami (Tohoku University). “So we found a digital method to adjust the behavior of the p-bits without the need for the large, clunky analog circuitry typically used.”
Their approach uses small electronic devices called magnetic tunnel junctions (MTJs) that spontaneously switch between two states in a random manner. By feeding this 50/50 random bitstream into a simple digital circuit that gradually combines the signals at controlled times, the team can smoothly adjust the probability that the output will be 0 or 1. Importantly, the same digital circuitry can also compensate for natural device-to-device variations in these stochastic factors, making the approach robust to manufacturing non-uniformities.
This approach enables two capabilities that have long been obstacles in hardware-based probabilistic computing. First, the system updates its internal state in a self-organizing manner. This means that various elements naturally avoid mutual interference. This allows many p bits to work in parallel without a central controller. Second, the design allows for a form of “on-chip annealing,” a method of gradually narrowing down the solution by changing the underlying timing settings rather than completely rewriting the stored parameters.
This remarkable new design developed by the research team requires far less area and power than alternatives, while also being compatible with modern semiconductor manufacturing. Researchers hope this advance will make probabilistic computing practical for applications ranging from artificial intelligence to logistics, scientific discovery, and future computing systems.
The research results were presented at the 71st IEEE International Conference on Electronic Devices (IEDM 2025) on December 10, 2025 (Japan time).
- Publication details:
title: DAC-free p-bit: asynchronous self-coloring and on-chip annealing
author: Kemal Selcuk, Navid Anjum Ardit, Corentin Delacour, Jared Quintana Silva, Nihal Sanjay Singh, Haruna Kaneko, Shun Kanai, Jui Wu, Yixuan Chen, Yusheng Chen, Ong Yi Qing, Kuoqing Huang, Harry Chuan, Hideo Ohno, Shunsuke Fukami, Kerem Y. Kamsari
journal: 71st Annual IEEE International Electronic Devices Conference (IEDM 2025)
Doi: XXXXXXXXXXXXX
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