The idea of a machine that can build even better machines sounds like science fiction, but the concept is becoming a reality as companies like Cadence leverage generative AI to design and validate next-generation processors that also use AI.
In the early days of integrated circuits, chips were designed by hand. More than half a century later, semiconductors have become so complex and their physical features so small that it is now possible to design chips only using other chips. Cadence is one of several electronic design automation (EDA) vendors building software for this purpose.
Even with this software, the chip design process is still time-consuming and error-prone. But with the rise of generative AI, Cadence and others are starting to explore new ways to automate these processes.
The latest example of this is Cadence’s ChipStack AI “super” agent, which was announced on Tuesday. The platform is designed to automate tasks such as coding designs, running test benches, creating test plans, and tuning regression tests to debug and resolve issues as they occur.
In other words, Cadence has built an AI code assistant for chip design. But while this may sound like just vibe-coding on a chip, the company claims the agent has enough guardrails to limit hallucinations.
“By leveraging intelligent agents that autonomously invoke our foundational tools, we are dramatically increasing our customers’ productivity in critical design and verification tasks while freeing up scarce engineering talent to focus on innovation,” Cadence CEO Anirudh Devgan said in a written statement.
If you’re worried that this is going to be a Terminator-like Skynet situation, don’t worry. AI may be used to design better AI chips, but there is still a long way to go to automate the rest of the semiconductor supply chain.
ChipStack is actually made up of multiple subagents, or what Cadence calls virtual engineers, responsible for IP design, verification, signoff, debugging, and system-on-chip layout.
According to Cadence, the agent follows a pipeline that starts by ingesting everything about the part being designed or tested, including specification files and design briefs. These files are used to form the mental model of the chip.
The agent then uses this mental model to determine which tests need to be completed and generates the necessary code to do so, perhaps incorporating feedback from engineers along the way. From here, the agent can call additional EDA tools, and when a fault is reported, the agent automatically generates debug code to resolve the issue as it occurs.
This feature doesn’t seem to be limited to Cadence’s own models. The company says ChipStack can be run on-premises using a customer’s preferred open weight model or using a cloud-based model such as OpenAI. For example, the company suggests that users may be able to use Nvidia’s NeMo framework to customize models to fit their specific design process.
Cadence claims the agent increases productivity by up to 10x, a claim that has already caught the attention of several major chip vendors including Qualcomm, Altera, and Nvidia.
The latter is perhaps the least surprising. Nvidia is understandably quite bullish about the prospect of machine learning and generative AI running on its GPUs to accelerate all kinds of design processes, including EDA.
Alongside EDA, the GPU giant has also developed frameworks such as cuLitho that speed up things like computer lithography by simulating physical properties to design better photomasks for chip manufacturing. This technology has already been adopted by major semiconductor equipment vendors and foundries such as ASML and TSMC.
Cadence isn’t the only EDA vendor venturing into the agent space. Nvidia revealed at CES that it is working with Siemens EDA to bring similar agent functionality to its chip design platform. Meanwhile, in December, Nvidia poured $2 billion into Synopsys, buying common stock to drive GPU acceleration across simulation workloads, including EDA. ®
