Memristive Crossbar arrays promise computational revolution by directly performing calculations in memory, offering significant advantages for applications such as machine learning and artificial intelligence. However, the weights representing valuable intellectual property, learning information built into these arrays, remain vulnerable to security breaches if hardware is compromised. Muhammad Faheemlan and Wayne Burleson of the University of Massachusetts Amherst address this critical challenge by developing integrated security mechanisms that protect these weights and establish verifiable ownership. An innovative approach incorporating keyed permutations and watermark protection columns protect critical data without the need for a substantial redesign of existing memory architectures, and simulations demonstrate robust protection with minimal impact on area, latency and power consumption. This task represents an important step in building a secure and reliable in-memory computing system for increasingly sensitive applications.
Despite its advantages, non-volatile memasters are vulnerable to security threats such as fraudulent extraction of weight stored when hardware is compromised. Protecting these weights is essential as it represents valuable intellectual property resulting from a long and expensive training process using large data sets. This approach is efficiently integrated with existing memorable crossbar architectures without the need for critical design changes, and is simulated with 45NM and 22NM technologies.
Memristor Security, Keying and Watermarking Techniques
Scientists have designed a robust security framework for memorable crossbar arrays to address vulnerabilities to intellectual property theft and malicious tampering. To rigorously assess these mechanisms, researchers adopted the widely known MNIST dataset and complex radio frequency dataset. The experimental setup involves simulating matrix vector multiplication in a crossbar array, using normalized analog voltages as inputs and measuring analog currents as outputs.
Researchers focused on predefined weights in structural and power delay simulations, prioritizing security overhead and circuit behavior over classification accuracy. Using one transistor and one memristor per cell, the team adopted a 1T1R cell structure to prevent unnecessary currents and ensure accurate weight adjustment. This configuration allows for accurate control of the memory staconductance representing the stored weight, making reliable calculations easier. To explain the effects of the nanoscale, scientists integrated detailed interconnection models into simulations to capture parasitic effects that affect signal propagation and circuit performance.
They conducted extensive simulations using HSPICE across three CMOS technology nodes, 45NM, 22NM bulk PTM, and 7NM Finfet PTM, to assess scalability and performance across different manufacturing processes. Furthermore, in this study, arrays of different sizes, 10×10, 128×10, and 256×128 were evaluated to analyze the effects of array dimensions on security overhead and circuit behavior. Keyed transparency, which obscures weight position via key-controlled row remapping, was implemented using triplet swap to create large keyspaces while maintaining a minimal increase in transistor counts for the 128 x 128 array. For added security, the watermark sequence is designed to mimic normal sequences of structure and behavior, with variable arrangements and dummy activities to blend into the array and avoid detection. A combination of these techniques provides minimal performance trade-offs and robust protection, demonstrating the potential to protect memory in-memory systems against sophisticated attacks.
Memristor's security, minimal overhead has been demonstrated
Scientists have developed a security mechanism for memory-based crossbar arrays, addressing vulnerabilities in in-memory computing systems and protecting valuable intellectual property built into machine learning models. Using realistic interconnection models and large radio frequency datasets, simulations of 45NM, 22NM, and 7NM CMOS nodes exhibit robust protection with area, latency, and power consumption of less than 10% overhead. Measurements check for a modest performance impact. A 256×128 array of 45nm nodes showed 8.
A 8% reduction in column current, a 5.5% increase in delay, and a 9.8% increase in power. Transistor count increased by just 2.34% when leveraging the triplet swap configuration, when highlighting the efficiency of the implemented security features.
These trends are consistent across smaller arrays (128×10, 10×10) and advanced technology nodes (22nm, 7nm), indicating the scalability and robustness of the approach. The study provides a practical solution to protect against unauthorized extraction of stored weights, as training costs for key machine learning models are projected to exceed $500 million by 2030. By obscuring the mapping of inputs and stored values, the mechanism resists ownership tampering and validation of support, demonstrating that effective security does not require critical security for performance or efficiency.
Memristor Security, Minimum Performance Impact
This study demonstrates the success of implementing security mechanisms within Memristive Crossbar arrays, a promising architecture for the acceleration of memory computing and machine learning. Simulations across multiple CMOS technology nodes, 45NM, 22NM, and 7NM, and array sizes consistently show that these mechanisms are efficiently integrated with existing designs, with minimal overhead in area, latency, and power consumption. The results show that both security features can be added to performance metrics with a less than 10% impact, indicating that robust protection does not require a significant trade-off in efficiency.
This is especially important given the increased costs of training large machine learning models and the growing need for secure in-memory architectures for next-generation computing systems. The team checks functional accuracy via multiplication of analog matrix vectors based on established power supplies. Further investigation is needed to assess the effects of process, voltage and temperature variations and optimize performance of larger crossbar arrays. Monte Carlo simulations are also used to analyze key design parameters. This research provides critical steps to building safe and efficient in-memory computing systems that address critical needs in the rapidly evolving field of artificial intelligence and machine learning.
