Memristors march | Nature Electronics

The search for new energy-efficient electronic hardware for machine learning and artificial intelligence (AI) tasks is at the heart of much of today’s electronics research. One such approach involves the use of two-terminal memory devices known as memristors. These devices can provide both information processing and memory in one unit and can be used to create various forms of neuromorphic computing. When incorporated into large crossbar arrays, they can be used, for example, to implement parallel matrix-vector multiplication operations, a core computation in many AI models.

Photo of the packaged cellular neural network chip developed by Qiangfei Xia et al.
Credit: Ali Abdel-Maksoud and Qiangfei Xia, University of Massachusetts Amherst

Although questions remain about the durability and maintenance of memristors,¹and the industrial feasibility of the technology.^{2, 3}device capabilities and applications continue to expand. And in this issue, nature electronicsHere are some of the latest advances.

Let’s start with research on cellular neural networks. Cellular neural networks are computing architectures that resemble the structure of the human retina, enabling massively parallel analog computations that are valuable in applications such as high-speed image processing. However, hardware implementations of such networks are typically bulky and power-intensive. Qiangfei Xia and colleagues now show that memristors can be used to build low-power cellular neural networks.

Researchers based at the University of Massachusetts Amherst, Rensselaer Polytechnic Institute, Milburn High School, and the University of Southern California, Los Angeles, will first create a Python-based digital twin for hardware control and network simulation. We then built a version of the network using transistors, followed by a version using multilevel non-volatile memristors, and showed that it can be used for image processing tasks such as edge and horizon detection. (Please also see the research briefing session regarding this research.)

Although crossbar arrays of memristors have shown the potential to perform parallel matrix-vector multiplication, inverse matrix-vector multiplication, a more difficult task for traditional computers, remains difficult. In another article in this issue, Piergiulio Mannocci, Daniele Ielmini, and colleagues report an in-memory computing accelerator for matrix-vector inverse multiplication.

Researchers based at Politecnico di Milano, Hewlett-Packard Research Institute, and Peking University are using static random access memory to fabricate the chip in 90 nm complementary metal oxide semiconductor (CMOS) technology. They show that the chip can be used to find solutions to systems of differential equations by recursive block inversion, as well as to track the trajectory of a rocket through a Kalman filter and to measure the acceleration of the inverse kinematics of a robotic arm.

A variety of neuromorphic systems with spike timing-dependent plasticity have been developed. Integrating synaptic fatigue dynamics, similar to biological short-term plasticity, into such systems has the potential to improve functionality, but hardware implementation is not straightforward. In a further article in this issue, Yuchao Yang et al. report the development of an interfacial dynamic memristor that provides high durability and cycle-to-cycle uniformity and can exhibit short-term synaptic fatigue plasticity.

Researchers based at Peking University, the Chinese Academy of Sciences in Beijing, and the China Brain Research Institute in Beijing have combined an interfacial dynamic memristor into a one-transistor, one-nonvolatile memristor cell with tunable spike-timing-dependent plasticity dynamics. This creates a hybrid synaptic element with plasticity that depends on the timing of fatigue spikes. These elements are used to construct a spiking neural network circuit that can be used for speech recognition tasks and exhibits better performance than traditional spike timing-dependent plasticity approaches.

Finally, there is research on human-machine interfaces, with Yuchao Yang et al. reporting a memristor-based single-spike coding system for use in such interfaces. This approach relies on a vanadium oxide memristor that precisely encodes information as a single spike, and a hafnium oxide/tantalum oxide memristor with a programming strategy that limits conductance drift.

Researchers based at Peking University, Southwest University in Chongqing, and China Brain Research Institute in Beijing have shown that the system can be used for real-time vehicle control from surface electromyography. Through simulation, we also highlight that it consumes about 38 times less energy and has about 6.4 times less delay compared to traditional rate coding systems.