The structure created between the two metal interconnect layers has four layers of tin at the bottom and SI-doped HFO.2ti removal layer, and tin on top.
Currently, this is a ferroelectric capacitor structure, but after a single electroforming operation (expanding the conductive thread through the oxidizing bacteria) results in a reprogrammable memorizer structure.
This allows you to freely create both devices anywhere on this layer.
“Ferroelectric capacitors allow for quick and low energy updates, but their read operations are destructive and unsuitable for inference,” CEA-Leti said. “Memorysters are excellent at inference because they can store analog weights, are energy efficient during read operations, and support in-memory computing. [However] Memlister's analog accuracy is sufficient for inference, but it is lacking in learning, which requires small progressive weight adjustments. ”
The idea in use is that off-chip training can be used first to program the inference model into the conductance of a set of member stars.
The IC then runs a learning algorithm that digitally stores the weights of the neural network in an array of ferroelectric capacitors, and uses these new weights to update the analog weights of the memorizer.
“The front and rear paths use low-precision weights stored in the analogue of the memorizer, but the updates are achieved using a high-precision ferroelectric cap,” says research leader Michele Martemucci. “Members are regularly reprogrammed [three] The most important bits stored in the ferroelectric cap. ”
A proof-of-concept device made with a standard 130NM CMOS IC includes 16,384 ferroelectric capacitor cells (each cell has one capacitor and one transistor) and 2,048 memorized cell (one memorized and one transistor).
10 capacitors store a single signed digital integer. Memories are operated in pairs and store differential (and therefore signed) values.
To avoid the need for DACS to transfer data from digital capacitors to analog memorizers, the three most important capacitors have an area (charge) ratio of 1:2:4 and use a simple analog sum to set the memorizer.
CEA-Leti collaborated with CEALIST, CNRS, CNRS, Bordeaux, Bordeaux Inp, IMS France, Université Paris-Saclay, and the Center for Nanosciences and Nanotechnologies.
For more information, read Nature Electronics Paper, “Ferroelectric Memory Memory for Both Training and Inference.” This clearly written paper can be read in full without paying.
The illustrations give the impression of a semi-physical artist. The sandwich has a capacitor drawn on it.
