RISC-V Pioneer Sifive has unveiled the second generation of its “intelligence” family, designed for machine learning and artificial intelligence (ML and AI) on devices at the edge.
“AI catalyzes the next era of the RISC-V revolution,” claims Sifive's CEO Patrick Little about the event of its latest launch. “There is strong traction, including the adoption of the new X100 series by two Tier 1 US Semiconductor Companies. Based on this momentum, a new second-generation intelligence IP has been built, adding new features and configuration to accelerate customer design and time to the market.”
The company's latest release comes a year after taking the form of its own IP built on a free, open source RISC-V instruction set architecture Intelligence XM Series Release – It was available, and stated that it could be configured as an accelerator for the artificial intelligence workload of the device, but as the only CPU in the system, “incorporating the host CPU.”
The second generation intelligence family includes the upgraded XM series Gen. 2, but at the time of Sifive's writing, it was not fully disclosed beyond the promise of 16 terra operations per cluster and 16 terra operations per second of architecture. [Large Language Models]”However, more information about the upgraded X280 and X390 Gen. 2 IPs, as well as a new entry-level design called X160 and X180 Gen. 2. Support for 128-bit vector length.
The second generation includes two all-new IPS, the X160 and X180 Gen. 2, targeting the Internet of Things (IoT). (📷:sifive)
The X280 Gen. 2 is on top of these with RVA23-compliant RISC-V implementation, support for 1, 2 or 4 cores per cluster, SV48 memory management unit, and support for 512-bit vector length. Finally, the X390 Gen. 2 adds support for the SV57 MMU feature and 1024-bit vector length. All new models include the Sifive Scalar Coprocessor Interface (SSCI) and Vector Coprocessor Interface Extension (VCIX) accelerator control interfaces, and loosely coupled vector pipelines that the company claims to avoid memory stalls.
All IPs are currently licensed, Sifive is not publicly available, but we are sure that the first silicon is expected in the second quarter of 2026. Detailed information is available. On the Sifive website.
