Method for generating a predictive circuit for classification of tabular data

Deep learning technology has become increasingly advanced over the past few years, reaching human-level accuracy in a wide range of tasks, including image classification and natural language processing.

The widespread use of these computational techniques has stimulated research aimed at developing new hardware solutions to meet the enormous computational demands.

To run deep neural networks, some researchers have developed so-called hardware accelerators, which are specialized computing devices that can be programmed to handle specific computational tasks more efficiently than traditional central processing units (CPUs).

Until now, the design of these accelerators has been primarily done separately from training and running deep learning models, with only a few teams working on these two research goals simultaneously.

Researchers from the University of Manchester and Pragmatic Semiconductor recently set out to develop a machine learning-based method to automatically generate classification circuits from tabular data, which is unstructured data that combines numerical and categorical information.

The method they proposed was Nature Electronicsrelies on a newly introduced methodology that the team calls “small classifiers.”

“A typical machine learning development cycle involves maximizing performance while training a model, and then minimizing the memory and space footprint of the trained model for deployment on processing cores, graphics processing units, microcontrollers, or custom hardware accelerators,” Konstantinos Iordanou, Timothy Atkinson, and their colleagues wrote in the paper.

“However, as machine learning models become larger and more complex, this becomes increasingly difficult. Here we report a method to automatically generate predictive circuits for classification of tabular data.”

The miniature classifier circuit that Iordanou, Atkinson and their colleagues developed consists of just a few hundred logic gates, and despite its relatively small size, they found it could achieve accuracy comparable to that achieved by state-of-the-art machine learning classifiers.

“This approach delivers predictive performance comparable to traditional machine learning techniques while using significantly fewer hardware resources and power,” Iordanou, Atkinson and their colleagues wrote.

“We use an evolutionary algorithm to search the space of logic gates and automatically generate classification circuits that maximize training prediction accuracy, consisting of up to 300 logic gates.”

The researchers tested their tiny classifier circuit in a series of simulations and found it to produce very promising results in terms of both accuracy and power consumption, and they further verified its performance on an actual low-cost integrated circuit (IC).

“When simulated as a silicon chip, our tiny classifier uses 8–18x less area and 4–8x less power than the best-performing machine learning baselines,” Iordanou, Atkinson and their colleagues wrote.

“When implemented as a low-cost chip on a flexible substrate, it occupies 10-75x less area, consumes 13-75x less power, and delivers 6x higher yields than the most hardware-efficient ML baseline.”

In the future, the miniature classifier developed by the researchers could potentially be used to efficiently tackle a variety of real-world tasks, such as as an on-chip trigger circuit for smart packaging and monitoring of various goods, and to develop low-cost proximity sensor computing systems.

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