Physical AI systems that enable machines to perceive, analyze, and respond to real-time environments are increasingly being deployed across edge, industrial, and automotive applications. This change is driving the need for more powerful and flexible semiconductor architectures that can support complex workloads such as vision processing, sensor fusion, and real-time decision making.
To address these requirements, Cadence is working with Samsung Foundry to expand its chiplet ecosystem while developing silicon prototypes built using Samsung’s SF5A process technology. This effort focuses on creating a scalable platform that supports physical AI workloads while overcoming the limitations of traditional monolithic system-on-chip (SoC) designs.
As SoCs become more complex, they face constraints in interconnect density, thermal management, and reticle size. Chiplet architectures, which divide systems into small, individually manufactured functional blocks and integrate them at the package level, are increasingly attracting attention as a way to circumvent these challenges. Chiplets enable heterogeneous integration, allowing designers to combine analog, digital, and AI computational elements without sacrificing performance.
This approach also supports design extensibility and reuse. Pre-validated chiplets can be deployed in multiple products, potentially reducing development time and costs. Power efficiency is another advantage, as individual chiplets can be optimized for specific voltage and frequency requirements, which is especially important for battery-powered edge devices. Smaller die improves manufacturing yields, reduces cost per unit, and supports higher volume deployments.
Physical AI workloads can greatly benefit from this model. Applications such as real-time camera processing, AI-enhanced radar in self-driving cars, smart manufacturing equipment, and sensor-driven systems often require high compute density, along with tight power and latency constraints.
Cadence’s specification-to-packaged chiplet ecosystem is designed to streamline engineering processes and accelerate time-to-market for chiplet-based solutions across the physical AI, data center, and high-performance computing markets. As part of the collaboration, Samsung Foundry is co-developing a silicon prototype of Cadence’s physical AI chiplet platform and integrating pre-validated partner intellectual property (IP) implemented on Samsung’s SF5A node.
“We are pleased to work with Cadence to demonstrate the competitiveness of Samsung’s SF5A technology,” said Tae-joon Song, vice president of foundry technology planning at Samsung Electronics. “Through this trusted partnership, we look forward to successfully expanding our ecosystem from chiplet specifications to packaged parts and helping our customers accelerate a reliable path to cutting-edge silicon solutions for physical AI applications, including next-generation automotive design.”
Samsung Foundry offers automotive-grade process technology from the 14nm node to the advanced 2nm node, and SF5A was selected for this project. The company said its automotive processes meet AG2 certification standards and incorporate automotive-specific design methodologies such as AEC-Q100-aware signoff, design for test, and functional safety support. Samsung also highlighted the role of design infrastructure, IP portfolio, and reference flows in accelerating development.
Together, Samsung Foundry and Cadence aim to provide a ready-to-use foundation, reduce development risk through proven IP, and deliver a pre-validated chiplet platform that supports flexible heterogeneous integration.
As the semiconductor industry continues to transition to multi-die architectures, this partnership reflects a broader effort to make chiplet-based designs a viable route to deploying physical AI across robotics, automotive systems, industrial equipment, and consumer devices.
