Readypower framework enables interpretable and convenient architectural power analysis

Accurate power estimation is a key challenge in modern processor design, requiring techniques that balance accuracy and computational efficiency. Qijun Zhang, Shang Liu, and Yao Lu, along with colleagues at the Hong Kong University of Science and Technology, are addressing this need using a new power modeling framework called ReadyPower. While the team identifies key limitations of existing approaches: unreliability, limited interpretability, and practical difficulties associated with machine learning-based models, they also acknowledge the inaccuracy of traditional analytical methods. ReadyPower overcomes these challenges by bridging the gap between theoretical models and real processor implementations by incorporating parameters at multiple levels of abstraction in a sophisticated version of the established McPAT model. This significantly increases the accuracy of the tool, resulting in over 20% lower error rates and better correlation to actual power consumption compared to machine learning alternatives on both the BOOM and XiangShan CPU architectures.

This work combines analytical modeling and machine learning to overcome the limitations of existing approaches by adapting to new designs and technologies without extensive manual calibration. This provides a more flexible and automated way to estimate power consumption during the CPU design process. AutoPower utilizes power group decoupling techniques to identify and model different power consuming components individually, simplifying the modeling process and improving accuracy.

By leveraging information from register transfer level (RTL) designs, transfer learning further reduces the amount of data required to train models for new CPU designs and enables pre-synthesis power, performance, and area (PPA) estimation to enable initial design optimization. The team collects data through simulation and sometimes real-world measurements to extract relevant features from the CPU design, such as clock frequency, voltage, area, and switching behavior. Machine learning algorithms such as XGBoost predict power consumption based on these features, and experiments demonstrate AutoPower's accuracy and efficiency, providing a valuable tool for computer architects and power estimation engineers.

Multilevel power modeling for modern processors

Scientists have developed ReadyPower, a new analysis framework designed to provide reliable, interpretable, and ready-to-use power modeling for modern processors. Building on the widely used McPAT model, this study addresses the limitations of both classical analytical models and machine learning-based approaches by systematically introducing new parameters at the architecture, implementation, and technology levels. The team designed a multilevel parameter system with architecture-level parameters that reflect microarchitectural design decisions, implementation-level parameters that capture register-transfer level (RTL) design-dependent power characteristics, and technology-level parameters derived solely from process technology libraries. This step-by-step approach enables accurate calibration across different design stages and technologies.

In our experiments, we used a known processor design to refine new parameter values, effectively learning discrepancies between the analytical model and the actual implementation. Results show that ReadyPower achieves over 20% lower mean absolute percentage error (MAPE) and over 0.2 higher correlation coefficient R compared to machine learning baselines on both BOOM and XiangShan CPU architectures, and maintains consistent accuracy even when the test data deviates from the training data distribution. The fully open source framework provides a ready-to-use solution for designers seeking accurate and interpretable power modeling capabilities, linking each new parameter to explicit physical parameters within the processor, allowing designers to understand the power calculation mechanisms.

ReadyPower accurately models the power consumption of modern processors

Scientists have achieved a breakthrough in power modeling for modern processors by introducing ReadyPower, a new analysis framework designed to be reliable, interpretable, and ready-to-use. Recognizing the limitations of traditional analytical models and machine learning-based approaches, we developed ReadyPower to bridge the gap between processor implementation and analytical modeling by incorporating architecture-level, implementation-level, and low-level parameters into the widely adopted McPAT model. The researchers generated 15 configurations for BOOM and 10 configurations for XiangShan and used eight different tests to simulate real-world workloads. Ground truth power labels were obtained through rigorous RTL code generation, simulation, and logic synthesis, and event parameters were collected through architecture-level performance simulation using gem5.

The data shows that ReadyPower consistently outperforms existing analytics and machine learning-based power models across all training scenarios. Averaged over these scenarios, ReadyPower has over 20% lower mean absolute percentage error (MAPE) and over 0.2 higher correlation coefficient R compared to the baseline method for both BOOM and XiangShan, providing a valuable tool for early power optimization and design space exploration.

Accurate power modeling across design levels

In this study, we introduce ReadyPower, a novel analytical framework for modeling power consumption in processor designs. The researchers addressed the challenges associated with adopting machine learning-based approaches, such as the limitations of existing methods, namely the inaccuracy and lack of reliability and interpretability of classical analytical models. ReadyPower improves accuracy by bridging the gap between theoretical processor models and real-world implementations by introducing parameters at the architecture, implementation, and technology levels. The team demonstrated that ReadyPower achieved significantly improved performance compared to both machine learning baselines and existing analytical models, with over 20% lower error on both BOOM and XiangShan CPU architectures, and high correlation with actual power measurements. In particular, the framework demonstrates strong transferability across different technology nodes and maintains accuracy even when applied to designs manufactured using different manufacturing processes. This work provides a practical and reliable tool for architects aiming to optimize power consumption in the early stages of processor design, and provides an attractive addition to existing methodologies.